Continuing the Scaling of Digital Computing Post Moore’s Law

Computer devices are nearing the limits of scaling traditional CMOS technology that up to this day follows Gordon Moore’s predictions for doubling transistor density every 24 months. In fact, CMOS scaling is now predicted to first slow down and eventually cease by the middle of the next decade (John Shalf, 2014) (Mack, 2011), with industry forecasting that technologies beyond 2 or 3nm may be infeasible or impractical due to cost, manufacturability, and the size of molecules which acts as a hard lower limit (Haron, 2008; Dhar, 2011). This approaching end of lithographic scaling does not mean the end of performance scaling for digital computing, but an invitation to identify novel methods to continue this scaling. Performance scaling will need to come with energy and cost reductions; without the density scaling they need to originate from novel architectures, technologies (devices and materials), or computational models.